9e216da9ef
After go1.16, go will use module mode by default, even when the repository is checked out under GOPATH or in a one-off directory. Add go.mod, go.sum to keep this repo buildable without opting out of the module mode. > go mod init github.com/mmcgrana/gobyexample > go mod tidy > go mod vendor In module mode, the 'vendor' directory is special and its contents will be actively maintained by the go command. pygments aren't the dependency the go will know about, so it will delete the contents from vendor directory. Move it to `third_party` directory now. And, vendor the blackfriday package. Note: the tutorial contents are not affected by the change in go1.16 because all the examples in this tutorial ask users to run the go command with the explicit list of files to be compiled (e.g. `go run hello-world.go` or `go build command-line-arguments.go`). When the source list is provided, the go command does not have to compute the build list and whether it's running in GOPATH mode or module mode becomes irrelevant.
162 lines
4.3 KiB
VHDL
162 lines
4.3 KiB
VHDL
library ieee;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity top_testbench is --test
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generic ( -- test
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n : integer := 8 -- test
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); -- test
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end top_testbench; -- test
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architecture top_testbench_arch of top_testbench is
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component top is
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generic (
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n : integer
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) ;
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port (
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clk : in std_logic;
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rst : in std_logic;
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d1 : in std_logic_vector (n-1 downto 0);
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d2 : in std_logic_vector (n-1 downto 0);
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operation : in std_logic;
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result : out std_logic_vector (2*n-1 downto 0)
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);
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end component;
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signal clk : std_logic;
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signal rst : std_logic;
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signal operation : std_logic;
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signal d1 : std_logic_vector (n-1 downto 0);
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signal d2 : std_logic_vector (n-1 downto 0);
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signal result : std_logic_vector (2*n-1 downto 0);
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type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
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attribute enum_encoding of my_state : type is "001 010 011 100 111";
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begin
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TESTUNIT : top generic map (n => n)
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port map (clk => clk,
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rst => rst,
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d1 => d1,
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d2 => d2,
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operation => operation,
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result => result);
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clock_process : process
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begin
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clk <= '0';
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wait for 5 ns;
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clk <= '1';
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wait for 5 ns;
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end process;
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data_process : process
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begin
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-- test case #1
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operation <= '0';
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rst <= '1';
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wait for 5 ns;
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rst <= '0';
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wait for 5 ns;
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d1 <= std_logic_vector(to_unsigned(60, d1'length));
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d2 <= std_logic_vector(to_unsigned(12, d2'length));
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wait for 360 ns;
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assert (result = std_logic_vector(to_unsigned(720, result'length)))
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report "Test case #1 failed" severity error;
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-- test case #2
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operation <= '0';
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rst <= '1';
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wait for 5 ns;
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rst <= '0';
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wait for 5 ns;
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d1 <= std_logic_vector(to_unsigned(55, d1'length));
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d2 <= std_logic_vector(to_unsigned(1, d2'length));
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wait for 360 ns;
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assert (result = std_logic_vector(to_unsigned(55, result'length)))
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report "Test case #2 failed" severity error;
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-- etc
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end process;
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end top_testbench_arch;
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configuration testbench_for_top of top_testbench is
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for top_testbench_arch
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for TESTUNIT : top
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use entity work.top(top_arch);
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end for;
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end for;
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end testbench_for_top;
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function compare(A: std_logic, B: std_Logic) return std_logic is
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constant pi : real := 3.14159;
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constant half_pi : real := pi / 2.0;
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constant cycle_time : time := 2 ns;
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constant N, N5 : integer := 5;
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begin
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if (A = '0' and B = '1') then
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return B;
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else
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return A;
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end if ;
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end compare;
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procedure print(P : std_logic_vector(7 downto 0);
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U : std_logic_vector(3 downto 0)) is
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variable my_line : line;
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alias swrite is write [line, string, side, width] ;
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begin
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swrite(my_line, "sqrt( ");
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write(my_line, P);
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swrite(my_line, " )= ");
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write(my_line, U);
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writeline(output, my_line);
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end print;
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entity add32csa is -- one stage of carry save adder for multiplier
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port(
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b : in std_logic; -- a multiplier bit
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a : in std_logic_vector(31 downto 0); -- multiplicand
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sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
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cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
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sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
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cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
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end add32csa;
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ARCHITECTURE circuits of add32csa IS
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SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
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SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
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COMPONENT fadd -- duplicates entity port
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PoRT(a : in std_logic;
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b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic);
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end comPonent fadd;
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begin -- circuits of add32csa
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aa <= a when b='1' else zero after 1 ns;
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stage: for I in 0 to 31 generate
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sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
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end generate stage;
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end architecture circuits; -- of add32csa
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