20 lines
265 B
Systemverilog
20 lines
265 B
Systemverilog
module toplevel(clock,reset);
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input clock;
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input reset;
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reg flop1;
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reg flop2;
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always @ (posedge reset or posedge clock)
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if (reset)
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begin
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flop1 <= 0;
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flop2 <= 1;
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end
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else
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begin
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flop1 <= flop2;
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flop2 <= flop1;
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end
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endmodule
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